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For now, we're moving forward with UVVM - it does what we need, is easy to use, and has sufficient documentation for us to get up and running with modest effort. The AXI4Lite BFM has some deficiencies, but meets our current needs, so we can get on with the real work. Thanks for everyone's advice.
Thanks - I'll take a look. Being a VHDL house, though, I'm reluctant to introduce any more Verilog or SV than I need to. Our synthesizable code AND testbenches are all VHDL. We pull in verilog when forced to by Xilinx IP, we but don't need to interface to it directly.
A quick update:
I spent about a day each with OSVVM and UVVM, with the goal of creating a simple testbench with a basic AXI4-Lite slave, using the provided AXI4-Lite Master. Within half a day, I had a self-checking testbench running on UVVM. While the example OSVVM testbench ran fine, I still...
Thanks.
I've rebuilt the entire set of Xilinx libraries for Active-HDL with the -na all switch. It was easy, once I found the Vivado config_compile_simlib TCL command:
config_compile_simlib -cfgopt {active_hdl.verilog.xpm:-sv2k12 -na all}
This got me past some SVA usage in the AXI IP, and...
So, I finally have a bit of time to look at OSVVM. I have the some of the AXI4Lite test benches running in Active-HDL. While there's a bunch of documentation for OSVVM, there doesn't seem to be any documentation for the AXI4 BFM portion. There doesn't appear to be a straight-forward way to...
It turns out that even the PE multi-language version of Active-HDL (VHDL, Verilog, SV) is incompatible with Xilinx VIP :| . It supports SV design constructs, but not the advanced verification constructs. Riviera-Pro would be needed, according to Aldec. There are app notes for OSVVM & UVVM...
I think we'll look for another BFM. What's interesting, though, is that Intel/Altera's Avalon BFM is SV, but provides a VHDL package for use in a VHDL testbench. Seems like it should be possible with VIP.
Thanks for the discussion, I've been out of active FPGA work for a couple years, doing embedded SW, so am trying to catch up to current tools. Active-HDL doesn't seem much different, but Vivado is a whole new animal, at least compared to ISE and Quartus. We have Active-HDL Plus Edition, I've...
Thanks, I'll take a look at OSVVM, looks intriguing. I don't *think* I'll need full AXI, except if I want to drive some Xilinx IP (EMC or VIP, for example). I'm hoping AXI Lite will be sufficient for our rather low throughput needs. The toolbox paradigm is attractive, rather than a framework...
We're looking at using Vivado for a new Series-7 design, and AXI4-Lite seems like the path of least resistance for our own IP. We're a VHDL house, and the BFM that Xilinx provides in Vivado, VIP, is strictly SystemVerilog.
I've written my own basic BFMs for Avalon-MM and Wishbone Classic...
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