Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
mnfsoft, the second link you provides comes in very handy and is a visual representation of what barry was trying to tell. I have a pretty good idea of what my output from the board needs to look like but im still not fully sure on how to code it to get this:
For a 36-element table between...
Hello barry,
Thanks for your response, your answer is very helpful. I guess my only issue at this point after make the table is not knowing how to include it in my code. I did a little more reading and saw that the simplest way would be to use a "case" module?
Either way thanks again you rock man!
Hello,
I am a newbie to verilog and just got a hold of a FPGA Spartan 3E board but now im in need of some help. Of course I have done a lot of searching and reading first. Anyways, the task I am faced with is to use a Look-up table to generate PWM that will be outputted into an RC filter which...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.