Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
warning:power:163
Hello!!
I want to measure the power consumption of some of my circuits that were designed in Virtex4 (XC4VSX55).I downloaded the latest version(9.1.02) of XPower Estimator from Xilinx.But when i import the map file then i always get the same power consumption and this doesnt...
SoC Encounter Question
Hello,
while i am working on a small design and after finishing In-Place Optimization and Nanoroute i check the geometry and i get a violation which is show in the picture below:
**broken link removed**
why is this pin unconnected? do you now any way to fix problems...
rtl compiler coding style
I have another question..now that i have to deal with cores that have a clock the script that i run in RTL compiler is the following:
read_hdl fpu_div.v
elaborate
dc::create _clock [dc::get_ports clk] -period 5 -waveform {0 2.5}
dc::set_input_delay 1 -clock {clk}...
rtl compiler
I would like to ask you a question about RTL compiler..
What is the difference between these two commands:
write -mapped > netlists/DP_FP_ADDER.v
write_hdl > netlists/DP_FP_ADDER.v
and which one is the best in order to use the extracted netlist in SOC Encounter?
Thanks in advance!
Hello!
I need some free IP cores(for example FP multiplier,FP divider) for my project..do you know any site that provides IP cores? i need cores which are as optimized as possible for FPGA and cores which are as optimized as possible for ASIC..
Thanks In Advance
i managed to solve this problem but now i get this when i type ./encounter:
**ERROR: Cannot open (for write) log file: "encounter.log".
Reason for error: Permission denied.
This version requires license using cdslmd daemon.
Checking out Encounter license ...
SOC_Encounter_GXL 6.2 license...
soc_encounter_gxl
Hi...I am a new user of EDA tools.I am trying to install SoC 6.2(the update release) on Ubuntu 8.04..
The install finishes correctly..
I added this line in the cshrc file:
set path = (/Cadence/SoC/tools/bin $path)
the file contains two more lines for the license:
setenv...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.