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Recent content by priyutiru

  1. P

    Silicon scan fails at high voltage

    Hi, What to do when scan chain fails at high voltages? How to debug? Ex: it passes at 1v but fails at 1.9v Thanks, Pri
  2. P

    Pattern count increase

    Will the pattern count increase with X masking logic in EDT compactor? What are some of the reasons for pattern count increase?
  3. P

    Test Coverage loss scan chains

    Why will there be test coverage loss when scan chains are increased?
  4. P

    Silicon Scan Chain testing

    Hi, What to do when scan chain fails at high voltage? (like it passes at 1 v but fails at 1.9 v), what are the ways to debug this? Thanks
  5. P

    Hold and Setup failures during Silicon Testing

    How to resolve Hold and setup violations during Silicon Testing on Test floor.
  6. P

    Lockup Latch during capture

    Hi, Lockup latches can help in hold time violation during scan shift. How about during Capture? Thanks
  7. P

    False and Multicycle paths stuck-at ATPG

    Hi, During stuck-at testing, what will happen to false and multicycle paths from the functional logic. Will stuck-at testing take them as faults? How does ATPG tool handle false and multicycle paths?
  8. P

    Lock-up Latch Question

    My question is if all the flops in the design are running at same shift clock say 20MHZ. In that case, do I need lockup latch? Lockup latch is used to prevent hold time violations caused by two different clock domains during shifting. In case if the shifting is same clock for all flops, do I...
  9. P

    Lock-up Latch Question

    My design has four clock domains( functional freq coming from PLL 250MHZ, 150MHZ etc), but during the shift mode, all the scan chains use low frequency 20MHZ. In this case, do I need lockup latches since the shift freq is same for all the flops in all domains? Only in the functional mode (at...

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