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Do you mean the switch should be closed at the time of de-integration?
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I have tried using a switch for the deintegration time instead of a resistor parallel to the capacitor. It looks like the circuit is not integrating at all. I have attached the waveform.
It is a dual slope topology instead of the control circuit I have given a PWL input. Integration time is 409 Us. I am initially doing the simulation for only one period as I will design the digital part later on.
I used the same circuit as in wikepidea.. My design is integrating but I want to get perfect saw tooth waveform. I have attached the schematic of my circuit.
Hello,
I have designed an integrator with 15 M resistance and 40 PF. The input is a single pulse with a width of 409Us and higher value is 700 mv and lower value is 100mv. The deintegration curve is exponential. How to make it linear?
Hello,
I will have to design a dual slope ADC with 11 Bits. Can anyone help me how should find the gain of the amplifier of the integrator so that I can design op amp accordingly. More over I am not sure how to find the range of input voltages which can give a conversion rate of 1k/samples...
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