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Recent content by princerock

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    help! glibc error for cadence ic

    glibc My os is Fedora Core 5 which has a new version of glibc (v2.4) Now the cadence cannot run with the following error message: relocation error: ../../tools.lnx86/bin/lmgrd: symbol errno, version GLIBC_2.0 not defined in file libc.so.6 with link time reference I think this is because the...
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    Problem with "change to layer" option in Virtuoso

    Hi, I'm drawing path in my layout (in Virtuoso) and find that the "change to layer" option is always "none". So I cannot change to another layer while drawing (e.g. to draw a metal1 path besides a poly one). How to solve this problem? Thank you in advance! princerock
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    How to calculate the 3rd harmonic distortion in Cadence?

    Hi, I'm designing an op amp and want to calculate the HD3. The input signal is 1KHz. I found that there's a "dft" function in the calculator. But how to set the variables in it? ("from", "to" means what?) And how to get the HD3 from the dft result? btw: how long should I run the transient...
  4. P

    Question about sigma-delta modulator design

    What is the relationship between quantizer levels and signal to quantization noise ratio(SQNR)? To increase quantizer levels we need to add more comparators, is this correct?
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    How to model input refered noise for Gm blocks?

    Hi everyone, I'm doing a course project about sigma-delta macromodel design. According to specs I have to add input-refered-noise to the ideal Gm building block (VCCS) in order to calculate the SNR. What confused me is, as the input-refered-noise is frequency-dependent, how can i model it in...
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    what is the phase margin in this case?

    Hi, I designed a fully diff op amp with cmfb. And when I did the ac sweep to the cmfb network I got the following result. I am puzzled by the phase response. Is it oscillating? If not, what is the phase margin? Thank you very much for your help! princerock
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    How to get the phase margin of CMFB in Cadence?

    cmfb simulation cadence Hi, I designed a fully differential op amp with CMFB. There is a requirement about the phase margin of CMFB in the specs. Then how can I get this from cadence simulation? Thank you for your help. princerock
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    Questions about CMFB for 2 stage op amp

    Hello, I'm designing a 2 stage diff op amp (folded cascode plus common source) and now I want to add cmfb to it. However I have the following quesitons before doing the design. 1. I have to add cmfb network for both stages, i.e. I need two cmfb networks, is this right? 2. DT vs. CT. Is...
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    help:how to simulate CMRR and PSRR in Spectra

    Hello, I think you should do the xf analysis. And when ploting your result, choose your diffirential input signal at first and the common mode input signal as second. Then you can use calculator to minus the above two curves (in dB). In this way you got the CMRR. For PSRR, just...
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    Beginner: How can I calculate Vds

    Consider a simple common source with active load circuit as shown below: Assuming all the transistors work in saturation and assign Vov=Vgs-Vt The output swing should be: Vdd-Vov1-Vov2 If I want a 2V output swing and Vdd=2.5v, then I can get Vov1+Vov2<0.5v Then according to other...
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    How to use SC circuit to implement the following expression?

    Y=(X1+X2-X3)*(1/(z-1)) X1,X2,X3 are inputs. z means in z domain. Use no more than 2 sampling capacitors and 1 op amp. I think this problem is the sc implementation of adder and scaler circuit. Where can I find materails about this? Thank you for your help!
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    hello, How to reduce 1/f output noise of amplifier?

    I think using PMOS instead of NMOS can reduce 1/f noise. Is that true?
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    what's good for learining BJT's and MOSFET's

    Gray's book is quite good, I think!
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    switched capacitor sample and hold circuit

    site:www.edaboard.com hold Agree with sunking. check your phase margin first

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