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Recent content by precession

  1. P

    A question about digital module timing constraint!

    Ah, I see, I see. Sorry, I made a mistake. Output_delay is the time needed before but not after the clock's active-edge. So negative output_delay value exactly means the hold time after the active clock edge, when the the min_path equal to zero. So, problem solved. Who can tell me how to delete...
  2. P

    A question about digital module timing constraint!

    Here is a depiction from Synopsys DC document. But I really can not understand why "min = min_path - hold". Let's think about the ideal case which the min_path equal to zero. In this case, the output_delay value is negative. Negative output_delay value means that the data could be changed...
  3. P

    abt Chip Synthesis Workshop, Synopsys

    download synthesis workshop synopsys Hi guys, I wanna get Synopsys Chip Synthesis Workshop lecture, urgently. But I have no enough points to download that ebook. HELP!
  4. P

    All Synopsys Tutorials

    synopsys ftp links Who can tell me how can I get Synopsys Chip Synthesis Workshop lecture. Thx

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