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I request you to please simulate the code ,it just lies in the post and see yourself. I am simulating the code in vivado xilinx simply . Simply saying you are simulating it wrong , doesn't make any sense . I think "dipin" has reached the point what I am asking.
thankyou..I am glad finally you reached at the result beacuse of which I started this thread. Now can you explain why i will have to give delay of 100 and above. Only if I give delay of 100 then I will see the correct outputs in post synthesis simulation. Why not less than 100 or any value below...
In behavioral simulation, I am getting result at next clock cycle.But after synthesis results get change, I see my output at 9th clock cycle.In Behavioral simulation , i get the output at next clock cycle.I want both the results to be same.
I suggest you to simulate the code and see yourself the...
Hii,
i am making module that compares two numbers using inbuilt operator of verilog. I am making the module synchronous with clock. The design is quite simple.After writing code the code and synthesising it which I have attached below I am obtaining the output at 9th clock cycle. I am expecting...
here in the image you can see the core cell and filler cells.
cells 330 and 329 are being overlapped , white boundary is filler 330 and green boundary to it is 329 .
This is the problem I am facing at each vcc core or ground core i.e. cells being overlapped
hello everyone.
I am doing floorplan for my design. I am using tcl file in ic compiler. One of the command is for creating corner cells and then one command is for creating vcc and ground cores.I am creating 6 vcc and 6 ground core cells. after executing these commands I see the CEL window and...
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