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Hi,
I have not studied MBIST workbook. But i have some expertise on MBISt. I have worked for few projects.
let me know What exactly you require regarding MBIST?
Bye,
Praveen.
how to delay the output and pass it as input
I agree with the above statements...
If you dont know the exact time for the signal to arrive at input port or output port, we will keep
keep pessimistic value of 60 % to the external world and 40 % to the chip
Re: set up and hold.
Setup & Hold is for a flop to capture stable value at its input.
for a flop its input may come from direct input ports of a chip or from output of another flop through combinational logic.
your signal must be stable at the input of a flop either it is coming from any...
Re: hdl questions
It is not a matter of synthesis or simulation.....
In Synthesis it will take a MUX and a comparator....so it will show X if u simulate synthesized netlist with
input 'X'.
But in rtl code it should give output '0'.
Praveen.
Hi,
U can download xilinx project navigator its a free trail version.
and start coding with any network concept like small protocols,
and run throgh the flow.
Praveen.
The use of verification language depends on the breadth of the project, available engineers and tools....
The languages like e,vera are already become porular as people are used to them.....
Now a days people are moving towards System verilog and System C, as many tools are suppoting these...
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