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Recent content by pratyusha

  1. P

    What about analog integrated circuit's future?

    Analog never be out of date. All the real signals are analog . so purely digital cannot make any sense. analog and digital interfaces are required. Analog cannot be automated fully like digital. analog will have very good future . All the best for u r bright future .
  2. P

    Analog circuit design tool

    cadence for simulation and layout. calibre for physical verification
  3. P

    What is the best book to start the anolog layout design?

    for beginners "IC mask design" by christopher saint and judy saint. this is very good book for easy understanding. After that " the art of analog layout" alan hastings . this is like bible for the analog layout designers. ALL the best[/b]
  4. P

    Creation of Dummy at the level of Layout

    In my case, the dummys' neighbours are not connncted to vdd r gnd. Shall I place the dummys a little far away from them?? ---------------- yes , u have to place individual mos device as dummy and maintain the same distance as matched devices. In layouts there is no rigid rules . we have...
  5. P

    Creation of Dummy at the level of Layout

    in practical , the layouts are not rectangular as we drawn. so the active region are not ending abruptly at the edge . It is diffusing and overlapping with the adjacent actives. so if we didn't maintain same dimensions this overlap may vary and cause mismatch. crosscoupled is one type of...
  6. P

    layout off grid errors

    our layout grid must be matched with the foundary grid. If we place any layer with the edges other than multiples of grid value. then it will we problem for the fab in designing mask for the layer . then it fails in generating the desired mask. So we cannot ignore OFFGRID errors.
  7. P

    What is Polygon and what is path in IC layout?

    Re: IC Layout we got offgrid errors while doing tapeouts and rectified them with polygons.
  8. P

    multi threshold cmos technology

    what is mtcoms MTCMOS is a low leakage , low power dissipation and high performance mos. it is used in burst mode application . check this link to know MTCMOS ":www.imec.be/esscirc/esscirc2001/Proceedings/data/70.pdf"
  9. P

    Why N-well Process but not P-well Prcoess????

    one of the reason may be , in design we use multiple positive voltages and common ground. so entire psub is connected to gnd and n-well can be isolated and connected to multiple supplies . but if we take nsub how can we connect it to multiple supplies. then we have to use twin well process which...
  10. P

    What is Polygon and what is path in IC layout?

    Re: IC Layout for path the width is set by default to the min width of that layer . it is very easy to draw for 90 degree . but for other angles polygons are used. with paths other than 90 degrees we get 'offgrid " errors
  11. P

    Layout of power switching NMOS and PMOS

    specially designed mos for handling high currents like "DMOS" are supported by some processes . we can use this special devices if available
  12. P

    Creation of Dummy at the level of Layout

    dummies are used to provide equal environment and during etching all the matched devices have to be etched similarly . In mos dummies the dimension of the device must be same to the matched device .In dummy mos all the three terminals are connected to power pins i.e vdd , gnd . You can...
  13. P

    layout problem in CADENCE tool

    "Multi stamp error ' occurs when all the gnd or vdd connections are not shorted . So check all the gnd connections are shorted or not.
  14. P

    Unbound devices in LVS checking

    cadence unbound pin IF u r using cadence - assura verification tool. go for LVS window. in that " Netlisting Option" icon will be there. if u click it another window will pop up. in that select " Use model property as device name if model in instParameters" after that click o.k and LVS

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