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In General,
Suppose you give AND cell as hier cell.
If the cell itself is failing, then it means the netlist and gds2 of Cell is not proper.
If the Failure is a top, you need to track the netlist/spice from the error report.
First of all, You need to confirm that the M4 spacing is 0.07u in Tech LEF.
Make sure to load the design again. restoreDesign (Assuming you are updating the Tech Lef directly - Initial File Only)
Now, coming to Encounter tool, move wire should move the metal based on the Manufacturing Grid...
Once you update the tech files, reload the design using restoreDesign command.
This should update the rules.
Unless you are having some DRC while routing the new route [reducing the space of metal], the change should be possible.
- - - Updated - - -
The new net to be assigned need to be in...
Here The violation is due to Maximum metal Density. The violations shows that the density must be less than some % with respective density window. [Correct Me if I am wrong]. You might want to have a closer look at the density of a metal in particular area/.
In your Tech File, you might have...
Are you trying to modify the routed metal? or the metal of Standard cell layout?.
If routed metal, then it should be possible manually (if you are looking at few cases)
whereas the Metal of Standard Cell layout can't be modified unless you regenerate the LEF/FRAM models after changing the layout/
For extraction, you use the parasitic models provided from the Foundry (Synopys - nxtGrd/ITF/TluPlus) .
Since, your LIB (db) file is with fF. This is golden to start with.
Tech File (in most case) won't have parasitic information required for extraction. You probably use the foundry parasitic...
I understand now. Thank you.
Can you please explain this statement :
"In fact the depth of diffusion contact is greater." . How and Why?
As the Di-electic width will be same over Poly and Diffusion.
Check the Cell Level Pin Placement.
1. Whether the Pins in the Cell Level have options for the router to route.
Eg: Output Pin Y, should have at-least 2 or more access point meaning where the Router can place the Via and make the connection)
This should be taken care
2. If the above is not...
The depth of this "hole" rather doesn't matter because etching process has to remove dielectric only. It is chemical or chemical and physical process. And it does not affect underlying layers.
I assumed the same as the Depth does not matter of the Contact Hole. But I did not have any evidence...
There should not be any Min Width related issues in PnR.
Check whether these DRC issues are in Cell Level or While Routing PnR?
PnR uses Tech Files (LEF/MW), so compare the minimum width rule in Tech File vs DRM.
May be TechFile is wrongly coded too! Again, To validate you have to run on TPT...
1. To check FILLER, please check your library level LEF file.
There for FILLER's you will define a particular CLASS
eg: MACRO FILL1
CLASS CORE SPACER ;
...
You can go through the different classes to understand the Category of the cells in the design
Adding from Comments @ThisIsNotSam :
2...
Understand.
We have the CONTACT size fixed (ie.. Hole Size is Fixed).
Also, Gate and Diffusion are not on the same Horizontal Plane during Fabrication.
Now, Metal have to be connected to Poly and Diffusion.
From Fabrication, The Depth of Hole required for Metal to Poly Connection and Metal to...
Looking into TechFiles and assuming Resistance will not be appropriate way.
But as Convention, more the Width less the resistance.
You can check the QRC/StarRC file which will have these information about resistance.
In your case, foundry might be old hence M1 is same as M5.
Usually, M1 will...
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