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Recent content by prady019

  1. P

    should the function and task which represent hardware be automatic or static?

    @laoruan can you please summarize about re-entrant task and function. Thanks in advance
  2. P

    [SOLVED] TCL testbench in Modelsim

    Thank you guys for your help. Compiling the .vho and then simulating it with TCL was good idea but for just small piece of code. I took the advice from trickydicky and followed it. After lots of errors i have converted my code in .vhd code and now i am going to write the testbench for the same...
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    [SOLVED] TCL testbench in Modelsim

    Writing a testbench is not a problem. The problem is instantiating the top level in my testbench and then compile it. It can be easily done when i have source code but i don't know how to include my top_level_design which is already been compiled separately and i am left with VHDL Output File (.vho)
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    [SOLVED] TCL testbench in Modelsim

    Thanks Tricky (.do) file is easy to handle. I am using the same for my TCL for now.:thumbsup: Hello Kevin i am getting your point but i dont have orignal source code. That's the reason i am using TCL to varify the design, so i am trying to dump data bus output in a text file then observe the...
  5. P

    [SOLVED] TCL testbench in Modelsim

    The correct way is to write an HDL twstbench, but i am bound to use the same my project where i have VHDL Output File (.vho) available with me. Extension vho is a output of Quartus(Altera) simulator tool for FPGA. And only tcl is the way i find to test the design. Now i am in some progress with...
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    [SOLVED] TCL testbench in Modelsim

    I have seen some threads about people seeking help in TCL scripts when you simulate a design on ModelSim without a testbench and i am one of them. I tried to write testbench but the design i am testing is very big and not fully known to me. So i was told to test few new functionality. :bang...
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    ModelSim "project compileall" how to set include directory

    You can include directory in verilog code itself by using `include and provide absolute path to your directory then compile the same.
  8. P

    FIFO depth required for async FIFO

    This is simple and best explanation i was looking for. Thanks Alaparthi
  9. P

    FIFO depth required for async FIFO

    This discussion helped me. Few months back i was asked question in interview "What will be minimum and maximum FIFO depth if write cycle is 80 words per 100 clock (80w/100clk) and read cycle is 8 words per 10 clock (8w/10clk) ?" And i was like not getting the question. can u help me guys. What...
  10. P

    How to calculate the depth of FIFO and what are the designs contraints for it?

    what will be fifo depth both minimum and maximum if write cycle is around 80words/100seconds, and read cycle of 8 words/10 second??
  11. P

    BT.656 video protocol

    Yes i tried, but that was a bouncer to me.
  12. P

    HD-SDI to BT 656 conversion

    Have any one done some implantation of conversion HD-SDI to BT 656 ?? Need to understand, how to process 20 bit parallel data to get BT 656 format image. Source format is HD-SDI. Thanks Do reply !!! :)
  13. P

    BT.656 video protocol

    yes before that i would like to get some more knowledge on BT 656 and SMPTE 292.
  14. P

    BT.656 video protocol

    ur effort is appreciable. i have this document, i read many document for this BT 656 n SMPTE 292. An this basic info is already extracted. i m receiving SMPTE 292 signal and after receiving this i have to decode to BT 656. so i want to get knowledge of SMPTE 292 decoder and then convert this...
  15. P

    BT.656 decoder specification

    ur effort is appreciable. i have this document, i read many document for this BT 656 n SMPTE 292. i m receiving SMPTE 292 signal and after receiving this i have to decode to BT 656. so i want to get knowledge of SMPTE 292 decoder and convert video signal to 8 bit BT 656.
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