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Re: Max freq of FPGA
Hi All,
Thank you for the reply.
Actually my question was not that.
Generally while selecting the device, fpga freq is one of the constraint. Also, as we move on from spartan to vertex family of xilinx, we see higher frequency support and "fpga frequency" would be...
Hi,
what is meant by max freq of fpga?
where to get the maxmum frequency information for a fpga?
I saw spartan 3 fpga datasheet. It is not mentioned in that.
Thanks in advance.
fifo size calculation
no delays are mentioned. But, as it is a asynchronous FIFO, read and write clks are not same(not in phase)...so FIFO is required. Need to calculate its depth.
fifo depth calculation
A FIFO has following data rate. What is depth of that?
incoming data = 80 words at 100 clks
outgoing data = 8 words per 10 clks
read clk = write clk
fifo data width = 1 word.
What is the fifo width for this configuration?
xor function using 2 2-1 muxes
Hi,
I did not understand the explanation.
Now, we have equations as XOR : Abar.B + A.Bbar
AND : A.B
OR : A + B
and equation of 2:1 mux is : Abar.S + B.S
So, how to come to a...
xor gate from 2 2 to 1 mux truth table
Hi Salma,
this is fine. This gives xor equation in terms of SOP. But now how select line is introduced to get effect of x or ing using mux ?
As you said, Shannon's theorem can be used. I want to know how to apply this logic to derive any gate from 2:1...
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