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Thanks crutschow, Just thinking that reduced common mode will reduce gm, that increases the mismatch contribution from the load devices. Considering the relation: (gm_diff/gm_load)*Vth_mismatch_loads
Hi, planning to design charge pump doubler, any ripple reduction techniques recommended would be helpful.
Are there any papers/lit that suggest ripple reduction?
High freq quantization noise means variation of signal after and before quantizer in time domain is higher and not signal is high freq.
After quantizer any way we have decimator and filter to cutt all higher freqs.
Your sim results are as expected. AC analysis doesnot kill dc sources, it will take dc points before calculating AC analysis data. You are not offsetting the opamp as you mentioned but giving common mode signal on dc 6V . Are u clear?
first thing is comparator and canb designed with low power consumption thats not a problem. Hyaterisis ll be around 50-20mv based on ur application. Ur trigger pt=1.3 so u can use nmos diffpair at input. U didnt mentioned del time in ur spec?
Yiu can find somuch data in books and papers for analysis. Iout and Iref need not have same value and its a high swing current mirror. analytically Gray and Holberg are better
Re: op amp question
Its the senario u r using this ckt for digital or analog application. Certnly its output bufer stage bcoz of high sizes and CS config. Csink and source txs are having high Gm s if u see it .
I think PSRR- is not necessary and if u do it it shows very less, bcoz only R's in that sig path..
in case of source ,sink ldo which is capable of providing i in both dirs then psrr from + and PSRR- id=s very imp concerns.
Re: Papers(tutorials) about step response or settling time o
first u go through control system analysis, pole zero concepts and then
go for Gray book , Its very helpful
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