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CPLD is XC9500XL family Device is XC9572XL. Package VQ44 Speed -10
Input to CPLD is Reset/25Mhz Clock
Output from CPLD Clock out
I have verilog Code in CPLD Clock out= 8.33 (25Mhz/3) no issue can read/write devices
I have verilog Code in CPLD Clock out = 12.25 MHz issue can not read/write...
My limitation is hat I can not change the hardware, all the changes need to happen in the verilog code, my only
input into CPLD is clock in= 25Mhz + Reset and clock out from CPLD. There are some timing issue this is
the reason I am trying to reduce the freq to 10Mhz.
This is my issue, I do not have a FPGA, I have a CPLD with limited resource. At this time, I can not change
the design. I appreciated if you have any other idea that you can share. Do you have any code that
allow me to go from 25Mhz to 10Mhz? thanks
I have a 25 MHz but need 10 MHz, will you please let me know how to write the verilog code for divide by 2.5. This is what I have done, but not sure if it will work. I have divide by 5 and multiple by 2.
always @(posedge CLK_OSC or posedge RST)
if (RST)
count<=0;
else if (count == 3'd4)...
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