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Recent content by playdc2002

  1. P

    What is the function of vinv and schmitt inside the VCO?

    Re: PLL There are a lot of papers in Razavi's PLL book.
  2. P

    Which book is better to start with?

    "Cmos circuit design, layout and simulation" by baker is better for starter.
  3. P

    PLL Theory, Texts, Thesis

    eda board charge-pump phase-lock loops razavi's first pll book is pretty good
  4. P

    Who is your idole in Analog Design?

    Bob Wildar allen
  5. P

    How much does LAMBDA equal in 0.18um process?

    define lambda for cmos device use simple nmos or pmos sweep the vds and w/L, get a bouch of vds vs Id curve, then you will have a rough idea about how much is the lambda
  6. P

    Can you pls introduce how to simulate the mixed signal?

    cosim verilog+hsim
  7. P

    Two questions about HSPICE

    HSPICE accuracy is dependent on models.
  8. P

    Info abt Analog IC design

    Allen's book is good for beginner.
  9. P

    ANyone read this book before ?

    That is a good complementary book if you already have gray and razavi book.
  10. P

    How to speed-up the simulation of PLL

    Try Hsim. for PLL simulation, usually, it is 2-4 times faster than hspice
  11. P

    how to generate a frequency variable pulse signal in hspice

    hspice pulse I want to generate a frequency variable pulse signal in hspice. For example, the nominal frequency is 50Mhz, at 2us, it jump to 51Mhz, at 4us. it drop to 49Mhz and so on. How to do it? Thanks!
  12. P

    Plot Gm/Id in Cadence Spectre?

    plot gm You can use the result browser to plot gm with dc sweep
  13. P

    Who is your idole in Analog Design?

    CMOS circuit design, layout and simulation by Jacob Baker is a good one for both digital and analog.
  14. P

    Who is your idole in Analog Design?

    CMOS circuit design, layout and simulation by Jacob Baker is a good one for both digital and analog.
  15. P

    How do we synthesize analog HDL?

    Re: analog HDL As far as I know, the high speed Digial cirucuit need full custome design instead of HDL-> synthesis flow. One good example is Intel's CPU. Using normal HDL-> synthesis flow, the CPU can not work at GHz.
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