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thx for help, but I need more help
I need creat a register ARCHITECTURE and adder ARCHITECTURE in same project, Xr and Yr must be taken from register
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY r3g IS
PORT (X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0)...
i wondering how create a register in witch i can write 4bits A input and 4bits B input. then take these data from register and sum them. sorry for my english
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