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Hi, Erikl
Thank you for getting the first reply here.
You mean that I should bulid a parameterized cell based on this model? It seems a little more complicated than i expected.
Sorry i forget to mention I don't have p-cell available from fab. So no process lib available.
I wanna find an ez way...
Hi, all
I get a RES model file like this way, and I want to use this model for spectre sim.
Since I'm a newbie in HSPICE area, I have the following questions.
1.which symbol I can use to call this model in analogLib? How to use it?
2.Should I need to change this RES model to 2-terminal model...
Any good idea to realize linearity tuning DCXO? It means frequency is monotonicity when control bits from minimum to maximum.
traditional switch capbank like we use in VCO is hard to achieve linearity tuning when using more tuning bits (12bits~14bits), bits from 011111111111 to 100000000000...
cl crystal capacitor
and for my question, brothers?
I just design a 26MHz xtal osc chips, shoulda use external xtal model, I just don't know the CL parameter in the quartz xtal manufacutre manual, it should be included in the xtal model for my simulation, or shoulda be inluded as my circuit...
32khz crystal capacitor
I'm not clear about the meaning of the crystal load capacitor CL.
As in the reference manual, the crystal has following parameters: Ls, Rs, Cs for the series resonance, Cp as intrinsic shunt capacitor, then what's the Load capacitor CL meaning?
1. As a crystal...
swicap,
fractional N pll can't gennerate stable fractional frequency, just frequency vary around the center of the fractional freq what i need.
Ask gain, anybody help?
If we get nmos from analogLib and appoint its model from TSMC PDK , the
simulation is good. But if we get nmos from TSMC PDK directly and also use
PDK model, the simulation is error. The information is listed as the
following. And the same file will be simulated well in other people's machine...
I need to design a divide by 3 or 5 circuit with 50% duty cycle with input freq= 3GHz, any prototype and valuable material are welcome.
Any suggestions?
since we can use all pass filter to compensate the group delay of the cascade stage of the low pass filter. I wonder if i can use higher order all pass filters to get better group delay? If we can, what's the defect of using higher order all pass filters?
I have learnt that Cadence don't support 64bit Intel x86 CPU and only IA-64.
I wonder if anyone could give me a resonable configuration of My hardware plateform whether server or PC, or give me some valuable advice on it. thanks!
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