# Recent content by pig8190

1. ### The question about design a radio to be used outdoor by using amp

I just curious that which family of transistor works best as an amplifier in a radio to used outdoors ? BJT, JFET, EM-MOS,NMOS, or DM-MOS ??? sometimes I just can't understand what different between these types and what require for designing radio. thank you very much:-)
2. ### Question for controller of test fixture

Hello, everyone .....if we want to write the test fixture for traffic controller, and then I put one Po(Power outage) mode to control light and the two RED light will blink. However, If I want two of sequence of stimulus into the test fixture: S0 => S1 => S2 => S0 S0 => S1 => S2 => S3 (10 clock...
3. ### Hello everyone, if i want write the state code in usa for using matlab,How ???

Hello.......I wondering that if I want to write the state code in usa for using MATLAB, how to I do ???? I kind of have some basic concept, I thinking that one input for putting code for state using 50 if-else statement (because usa had 50 states) .....did I head the right track ??? If...
4. ### Question for Frequency divide by 3 of 33% and 50% duty cycle

thanks so much for u guys help !!!! Really appreciate that !!!!
5. ### Question for Frequency divide by 3 of 33% and 50% duty cycle

I just trying to do 33% of duty cycle, but when I just run waveform, and my clock doesn't work........can u tell me how to solve it ???? thanks again!!!!! Did I head the right way to this kind problem??? module div3_a(clk,clk_out); input clk; output clk_out; reg [1:0] cnt_p...
6. ### Question for Frequency divide by 3 of 33% and 50% duty cycle

1. Design two frequency divide-by-3 circuits, one with output div3a (33% duty cycle), the other with output div3b (50% duty cycle). You can use rising-edge and falling-edge FFs in your designs. Write the verilog code to generate div3a and div3b. Write a test fixture and capture the waveform...
7. ### I have a question for design two frequency divide by 3 circuit in verilog !!

1. Design two frequency divide-by-3 circuits, one with output div3a (33% duty cycle), the other with output div3b (50% duty cycle). You can use rising-edge and falling-edge FFs in your designs. Write the verilog code to generate div3a and div3b and Write a test fixture??? Pls help me for...