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Hi everyone,
Has anyone had experience with post layout mismatch monte-carlo simulations with TSMC kit? I am using the 65nm process and is unable to perform the post layout mismatch simulation. I am able to do the mismatch simulation in schematic. However, when I tried to extract the parasitic...
Hi,
Thanks for the quick reply. We actually need to probe the signal directly on an IC pin using an active probe. The kind of stuff we are looking for idealy would somewhat be similar to Agilent N2784A but obviously with less cost.
Pierce
Hi everyone,
Does anyone has a good suggestion on a reliable probe positioner (hopefully less $$$)? My group is working on a project right now that requires moinitoring a signal on an oscilloscope over a long period of time and it would be very handy if we don't have to hold it manually...
45nm 65nm performance
Hi,
First of all thank you for your replies. As timof mentioned, it does seem that 30% is not unusual (especially for complicated logic gates such as XOR).
To Timof:
Can you please elaborate a bit more on how the transmission gate can be particularly sensitive using...
40nm performance gate delay
Hi,
I am working in 65nm technology and I have a problem with the post layout and schematic performance difference. Take an example of the conventional transmission gate based mux, the post layout simulation has a performance degradation of at least 30% over the...
Hi everyone,
I am working on a project right now that involves with a FM modulator and a frequency discriminator. The output of the FM modulator goes into the frequency discriminator consisted of a Dual Modulus Divider (DMD) and a Digital Flip Flop (DFF). To determine the dynamic range of this...
Re: How to measure two signals with a delay of less than 1 n
Hi,
Can you please elaborate more on the time to voltage for single event measurement? Are you referring to the time to digital converter?
Pierce
Hi everyone,
I am wondering if anyone has tried to measure two signals with a delay difference of less than 1ns? I am working on a high speed digital circuit right now and the delay from the rise of CLK to the rise of output is less than 400ps.
Ideally, I would like to see this on an...
Hi everyone,
First of all thanks for the replies. I was told by another graduate student that one way to complete this task is to first write up the verilog code (ex modelsim) then convert it to the gate level design with synopsys design vision. After this I believe a schematic/layout can be...
verilog to layout in mentor graphics
Hi everyone,
I am wondering if it is possible to write a vhdl/verilog code and uses it to generate the schematic and layout so that I can combine it with my own full custom design?
For instance, say I am working on a adder. In order to test the adder, I...
NAND gates is more preferred than NOR gates because of sizing.
NAND is NMOS in series and PMOS in parallel, while NOR is the other way around.
As people have already mentioned, the mobility of hole is less than that of the electron. Therefore, to achieve the same delay (current capability)...
Hi,
The number of gate inputs to CMOS gates is usually limited to four for both sizing and delay factors.
Lets look at the simplest NOR gate (complementary logic) as an example. it is essentially 4 PMOS in series and 4 NMOS in parallel.
Now, the more transistors you have, the more...
A.. Anand Srinivasan is right. The more output transistors (we call it fan out devices), the more capacitance. I am not too sure about Analog IC, but in digital IC it is often a better practice to limit the number of fan out devices to be less than 4 whenever possible.
gate length
This is my little 2 cents.
The drain current is proportional to the W/L ratio. Therefore, it is a better practice to just adjust one parameter, and i guess the common practice is to keep L at minimum level and adjusting W accordingly.
varying the gate length will definitely...
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