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Recent content by phy_des

  1. P

    What does '8M' refer to in : 0.13um Logic 1P8M Salicide?

    hi all what does '8M' refer to as per this : 0.13um Logic 1P8M Salicide
  2. P

    The implementation and the limitations of staggered and inline placement of pads

    dear all.... i just wanted to know about the implementation along with the limitations of staggered and inline placement of pads.Is it foundry dependent? can anyone help me out ? thanks and regards aswin
  3. P

    What happens when wire length decreases ?

    Re: wire length thank you friends..... inductance never came into my mind ...... thank you you are very much true but the thing is i dont want to reduce my netlength by adding buffers rather i would like to specify through commands....... consider i am using it for noise analysis .... then in...
  4. P

    What happens when wire length decreases ?

    wire length dear all............ just wanted your views on what happens when wirelength decreases...... the things i know are since length decreases delay decreases and less congestion ..... regards aswin
  5. P

    Looking for information about OCV

    Re: OCV dear lakshman..... thanks a lot.... the document was really useful..... regards aswin
  6. P

    Looking for information about OCV

    dear all..... i need to know about "on chip variation" can anybody help me out? thanks and regards aswin
  7. P

    The relationship between the resistance of a wire and its thickness

    Re: resistance consider a case where in there is a wire of width 64µm and four wires of width 16µm stacked one above the other...... can anyone just tel me what would be the relationship between the two cases in terms of resistance.....
  8. P

    The relationship between the resistance of a wire and its thickness

    dear all i just wanted to know the relationship between the resistance of a wire and its thickness?what happens to the flow of current? thanks and regards aswin
  9. P

    Power open during pin tapping in floorplanning

    Re: pin tapping hi chetanbs....... all the pins are associated with the respective nets and also the ports are declared before associating ...... the problem is the internal pins like the FP,VSS:,VDD:......... etc are not tapped to the respective nets........we can route them manually but...
  10. P

    Power open during pin tapping in floorplanning

    hi all.... during floorplan...inspite of declaring all the pin access points of pad cells.... there is power open during pad pin tapping ...... what could be the reason regards aswin
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