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Thanks everyone for your contributions. I feel that I'm starting to get an understanding on estimating time. Both perfectionism and abandoning bad designs are forms of wasted time. The goal seems to be to remove the wasted time. Perhaps it can be summed up as 'OK is good enough' and 'give up...
Thanks everyone for your contributions
dick_freebird, thank you for your input and being so honest.
It does seem quite a challenge, estimating how long a design will take. Is there anything you have learnt from your experience which has helped you estimate effort and schedule better? I...
keith1200rs,
I know the feeling of finding something last minute in verification -- it's a real pain, especially when it's something that should have been spotted earlier. I've kicked myself a few times, when problems have been found late (nearly always to do with interface between blocks or...
Keith1200rs,
Thanks for your response. This is the kind of thing that interests me. I agree that breaking down projects into smaller blocks is very important. And that top-level layout and final verification do take considerable time. Do you find you normally meet project deadlines? Do...
This may be slightly broad, or off topic, but how can one estimate the time a circuit will take to design? I have heard various estimation methods, such as 1 week per schematic. What do you do to estimate design time? Is this something that can be learnt from experience? I'm really looking...
Noise is calculated at the output then referred back to the input via a transfer function. It is good to check the transfer function is meaningful. The "Total equivalent input noise" plot may be trying to refer noise to a disconnected net with a transfer function of 0 (-inf dB). This would...
Hi Yangyang10182,
You're thinking in the right way! Most digital logic works on either a rising edge or a falling edge. Since this switched-cap circuit uses both rising and falling edges, you have to find a way to do this. If you clock it at twice the frequency then each alternate clock...
I am guessing the AD8021 has a BJT differential pair input. This is why there is such a large input current and low input resistance. How about using a different opamp with a FET input. This would provide far higher input impedence
I currently run process corners using custom made batch scripts for Eldo. The scripts add the library paths and parameter setup to the start of a .cir file. I then run the all the .cir file varients and extract/sort the results. I have looked at using the .alter command but it seems to not...
You could use Mosfets as resistors or capacitors. Both add distortion so it depends on your linearity spec. The resistors and capacitors can probably be traded-off against one another. The larger the resistors, the more noise but less area (as the caps can be reduced in size).
It's just a question of delay. You could clock the digital at twice the rate, with alternating clocks representing a rising edge and a falling edge. You could ignore the half cycle delays, since that is all they are; they do not effect the transfer function. If you are taking out taps at...
That is the 2nd harmonic. Is it a differential design? If so, the layout is not symmetric and introducing differences between the positive and negative sides.
The half delay is due to the output being delayed by half the clock rate. That is, it is valid by the falling edge of the clock if the switched-cap circuit is clocked on the rising edge. If you trigger the first switched-cap integrator on the rising edge the the second switched-cap integrator...
Hi,
Matlab version are often not fully backward compatible. There may be a few lines in the code written for R2006a that need to be adjusted. Have a look at the error messages and see what they say to do. Also have a look at the code in the editor, as it gives help on syntax error. Matlab...
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