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Recent content by phen3x

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    Assura LVS 616 in CentOS 7 (?)

    Hello everybody, does anyone have experience on working with Assura on Centos 7? Assura DRC is working fine, however LVS fails due to syntax errors after opening the .csm and .cls files for comparison. I know that Centos 7 is not supported, but using a 20 year old OS even in a virtual machine...
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    Ansys HFSS COM Engine non-responsive

    Hello all, I have a problem with Ansys Electronics Desktop 16.2. When I try to simulate a model, the COM engine starts but immediately becomes unresponsive. The error I get in the message window is: [warning] Com Engine non-responsive since 22:23:31, September 08, 2015. Can be due to CPU...
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    hfss design error-mesh matching process failed

    Maybe there are some solids oversubscribing each other, or a ***** somewhere.
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    How to simulate .gds files in HFSS

    You have to add the excitations (lumped ports or whatever you need), an airbox, radiation boundaries off the top of my head. Start with those and you will get into it! Have fun!
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    Linking HFSS and Matlab

    You could give a go to this: https://code.google.com/p/hfss-api/ Have fun!
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    Scripting in HFSS - particulary Python if you have used it.

    As far as the installation is concerned, HFSS 16 seems to be running fine in Centos 7. I needed to install it twice though. I am thinking of using IronPython myself, VBS is a real pain in linux (and in general). Do the Ansys material on scripting help at all or is it a waste of time?
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    HFSS v16 Error reading the vmesh Setup1

    Hello everyone, I have encountered a funny error in Electronics Desktop (HFSS16). While the simulation works fine the first time, the second time I try to run it without deleting the results I get an "Error reading the vmesh Setup1". Moreover, when I try to plot the mesh or the the e/m...
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    Clock dominates latch-type voltage sense amplifier output

    Indeed I am simulating with Cadence Spectre, so these practicalities don't really apply in that case.. For me the weird thing is that I even get spikes from the clock before the differential input on my input signal, while the clock is placed inside the latch comparator...
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    Clock dominates latch-type voltage sense amplifier output

    Hello guys. I am trying to create a voltage comparator, but in the circuit I am using the clock seems to dominate everything that happens, even the signal before the differential amplifier input. Any thoughts as to what might be going on?
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    [SOLVED] HFSS Angle Parameter

    Hello everybody. Does anybody know how to input an angle parameter in the design in HFSS? I mean, there are all kind of automated drawing shapes, but none accepts an angle as a design parameter. What I need to do is draw a parametric orthogonal triangle.. Is there another way to do that besides...

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