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Recent content by phaneendra.raguru

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    Synthesisable Array initialization of static values in Verilog

    Hi, i need an array of static values such as reg [7:0] s_box [0:3][0:3] = '{'{8'h0,8'h1,8'h2,8'h3}, '{8'h10,8'h11,8'h12,8'h13}, '{8'h20,8'h21,8'h22,8'h23}, '{8'h30,8'h31,8'h32,8'h33}}; It is...

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