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Recent content by petrelflying

  1. P

    Help me fix my synthesizable Verilog code

    Verilog question HI,siva_7517: first, you have to define the size of array in_buf_re and in_buf_im Added after 1 seconds: HI,siva_7517: first, you have to define the size of array in_buf_re and in_buf_im
  2. P

    how is realation between time and frequency domain?

    the convolution in time domain is a multiply in frequency domain, and the convolution in frq domain is a multiply in time domain the preperty and advantage is the most obvious
  3. P

    Verilog synthesize errors: multi-source in Unit on signal

    synthesize problem befor synthesize, you can use Nlint to check your code and find this error
  4. P

    how to simulate and verify a DSP or CPU hardware

    Now, we had design a CPU hardware for studying having similar structure as ARM. How can i simulate and verify its function? We have no enough time to write a C model to simulate its behaviour. Is there any other ways? THX Added after 13 minutes: We especially want to know the values of the...
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