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Sorry I picked the wrong code in the previous code here is the right one:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity spi_forum is
generic(N: integer := 8);
port(
clk, reset, W: in std_logic;
data: in...
Thanks! I can see clearly sync reset but I need to read some more on the async one in order to be able to implement it
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Now I have changed a few things, one I do count inverse but from that to force 0 or a value Its a bit of semantic so I need to learn a bit more to...
Sorry I see now the problem I know if you do something like counter_8clk > "1000" it does count until 8, now I can see previous it was a if condition with a process and now it a logic evaluation so as soon as we are in 8 will reset right the way.
there is going to be one type of reset one way...
:-) , no I am doing all exactly the same as post #47, but all in multi-blocks
The code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
entity upcnt8 is
port(
cnt_en : in STD_LOGIC; -- Count enable --...
Its a shame that lots of people have seen this post and only a few have comment/help :-(!
Today I implemented the same code onto 4 hdl files, one universal counter, universal_shift register, clock/38, and top with stage machine and logic.
I got to say it was a bit hard, I need to look at my...
Its true, I give you that, when you are coding with multi block and something is does not work I feel like a headache is coming when you change an condition and you have not clue where lie the error I feel I have to start to trace block by block and can be difficult to visualize.
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I created that new all in one code from the only purpose to show to people where asking for code, I know may be easier to point an error by rewrite the code but I think you missed the thinking, that all code is an summary from 4 vhdl files. That is why there is extra function in the shift...
that is an output, it's linked on ---> clock_38 <= oneUSClk;
That is why I didn't wanted to paste code as I am interested on principal and coding style more than have a code to do the SPI.
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Thanks for this code first of all, my first impression woow is there any more, I...
If you notice I am using a tick signal from that counter! What do you suggest?
Also from the datasheet I am attaching a transition requirements:
Would you still send a tick signal?
Sorry about the thought of negative edge, that was wrong? the register would move in half cycle.
Ok I really change the code just to please some people about using tick and evaluate at main clock, to be honest I only have to change counter_to_8 as the rest was evaluated on that way.
Now I have...
I am implementing as suggested it, but the need to clock/38 and second device assess data at positive edge of that clock is requirements I cannot change that.
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UPDATE:
I though a bit more about that problem and I also suggest to move the stage machine with a tick signal not...
The clock_38 can be easily fix by making resent to "100110" and not to "000000"
here is simulation:
Now if you notice data out is wrong because shift register is ticking over by clock_38_tick1'event and clock_38_out_tick1='1'
as you can see from the simulation here:
Also I try to changed...
Sorry for the delay here I tried to spend some time traing to do it with a running "clock/38"
and its possible but I am getting delay introduced from the processor and shift register which creating an unwanted delay
which make all more difficult, I solved it by add delay process and some logic...
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