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Recent content by PekingBoy

  1. PekingBoy

    calculation of net delay..........

    Hi, i think u can calculate the net delay as the follow: Logic level * T(Delay of LUT).
  2. PekingBoy

    Help require on verilog

    Thank you,everyone. I think icelucent is right.
  3. PekingBoy

    Help require on verilog

    Hi,i got a verilog file as the follow, ... case(f4Cnt) 'd0: begin a <= b+1; f4Cnt <= f4Cnt+1; end 'd1: begin a <= b+1; f4Cnt <= f4Cnt+1; end 'd2, 'd3, 'd4...
  4. PekingBoy

    Somethinng wrong with my code

    Hi，i think there are some errors in ur code,like syntax error,not-good coding style. Mixed single and double-edge expressions are not supported. What's more,the variable 'i' does not work as you wish. Only combinational logic can't implements your function in this way,a CLK is needed. Hope i...
  5. PekingBoy

    We are all from China

    Re: From China Hi,all. I am from Beijing, a FPGA designer. Hope to make frens with u and learn each other. Welcome to Beijing Olympics. Best regards.
  6. PekingBoy

    Difference between Logic cell & Logic gate?

    the logic cell of xilinx FPGA is called Silce,which contain 2 flipflops,2 LUT4 and some logic gates. Thanks and Regards
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