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Hi,
I am trying to perform simulation using a tensilica processor. I have seperate ram.dat and rom.dat files. When the first store instruction is encountered in the ROM, i get a multihit exception in the data tag array. I would be thankful for any suggestions as to how this can be...
HI,
I have been implementing a design with Astro.After CTS my design meets timing and I tried to add filler cells before routing the design.But once filler cells are added the utilization goes to mode than 100% resulting in an error.Is there any command to stop adding filler cells after a...
Hi,
Could anyone please advise regarding the creation of a CDL file in Cadence ICFB.I have the technology lef file and also the technology verilog file.I hope to create a CDL file for the technology.I have not been able to find a way to do this.Is there any other way to convert a verilog/lef...
HI,
I have been trying to implement a large design. I have synthesized it using Design Compiler and then checked the initial timing in Jupiter without interconnect and found no max cap/ max trans violations. After placing the design in Jupiter ,I had some cap and transition violations . Using...
tlu plus
Hi ,
Thanks very much to both of you. I have found that I might have to run a script to modify the SDF as the intial libraries were setup for sdf from PT.
I pulled out the ITF file from the .nxtgrd file and generated the Tluplus models.I was...
tluplus
HI,
I have been trying to work with Physical Compiler and Astro.I am now required to use Tluplus models as part of a flow that we want to run.
Could somebody let me know if there is a seperate Interconnect Technology File for each condition max,min,typical or is there a way to generate...
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