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Recent content by pcbeng25

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    [SOLVED] Continuous sampling 3GSPS ADC and Altera FPGA interface

    To update. I did get the data into RAM and I am correctly creating a Histogram now without missing samples and without overflowing the FIFO. In fact, I have to have pauses when reading the data out of the FIFO to avoid underflow. Now I can move on to my processing algorithms. I want to...
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    [SOLVED] Continuous sampling 3GSPS ADC and Altera FPGA interface

    The DPRAM right now is 16 bits wide...may make it wider depending on how many samples we require for an accurate representation of our data...still yet to be determined, but that is an easy task. I like the idea of duplicating the writes to a second set of DPRAMs and using both ports (one for...
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    [SOLVED] Continuous sampling 3GSPS ADC and Altera FPGA interface

    Ok, so it seems if I take 32-bits out of the FIFO instead of 64, then have a 5 stage pipeline, I will require 20 DPRAMs in order to store the data. The post-processing will have to sum the locations in those 20 RAMs into one complete histogram. Reasoning for this: one 32-bit read from the...
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    [SOLVED] Continuous sampling 3GSPS ADC and Altera FPGA interface

    Sorry I haven't replied...for some reason I have not received any emails that this thread was updated. I will look over the replies and see what I can do. I appreciate the suggestions. Now I just need to map this out a bit and see where it gets me. I have been trying to figure out how to...
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    [SOLVED] Continuous sampling 3GSPS ADC and Altera FPGA interface

    well what can I say without upsetting the lawyers...Basically I am not allowed to say too much. I am using the data from the ADC as an address to a DPRAM, then incrementing the contents to create a histogram. The FIFO only gets 32 bits written into it (one of the 4 samples on the output of the...
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    [SOLVED] Continuous sampling 3GSPS ADC and Altera FPGA interface

    I'm currently writing an interface for a 2.5GSPS 8-bit ADC connecting to an Altera Stratix III FPGA via 32 LVDS lines. The data rate is 625MHz on the input to the FPGA, and it is deserialized 1:4 for an internal data rate of 156.25MHz. I am currently feeding this data into a FIFO. My dilemma...
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