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Hi all,
Currently I am simulating my opamp loop gain char by using stb analysis. The simulation results looks good for pre-layout simulation and also post layout simulation extracted CC. The problem happen when I use RCC, RC and R extractiion netlist for the post layout simulation. The phase at...
hi all,
have a basic question here. I am studying one IO pad design, NMOS and PMOS driver is used as an ESD device. But, I don't know why only NMOS driver has ballast resistor (nwell res). Why PMOS driver doesnt have it. Appreciate ur help!
triode region
hi all,
I hv 1 question. In my current relaxation osc design, I hv 1 PMOS operating in triode region. this PMOS is cascoded on top of the other PMOS that serve to compnsate the process variation. My question is that, what is the purpose of the triode region MOS.
Or maybe you...
Re: Scaling VDD
thanks leo.... I am using relaxation OSC.... the variation is increased about +/-10% when I lower down operating VDD from 3V to 1.8V..... I did a minor chnages on the biasing.....
Scaling VDD
All,
What happen to the variation of the design (say OSC) if I use 1.8V VDD for my 3V transistor. One thing for sure we need to watch out for headroom. If the headroo is OK, what else can contribute to the high variation of the design across temp, process and VDD. (PVT)
thanks in...
hi all,
need help to answer below questions:
1) for stability analysis, which gain that we plot: open loop gain or loop gain?
2) Is phase margin and UGF will change after we close the loop?
Thanks
ldo simulation
Hi all,
Currently I am designing LDO.... I hv question regarding ac simulation.... do we need to include bypass capacitor in the simulation? As we know this capacitor is huge.... will this capacitor will be our dominant pole?
Thanks
calculate gate oxide capacitance
look for cgso, cgdo and cgbo value... also translate tox to get cox..... to get details explanation refer pls refer to BSIM3 manual from Berkeley website
Re: Resistor Voltage Coeff
it is not modelled..... anyway, voltage coeff shud be small for poly res.... if u using island res, then the v coeff quite significant (relative)
Re: Resistor Voltage Coeff
all resistors have voltage coeff..... it depends on the foundry process that u use.... for my case the salicided has higher vco.... u can do a quick check by checking the value for vco1 and vco2 in the model and compare the value...... higher value will have higher...
capacitance measurement of mosfet
I am not sure what is exactly ur test structure looks like..... but if u use 10/10 array, then the test structure is very big in order to get a reasonable capacitance value from your measurement..... u hv to makesure the capacitance value from the easurement...
apply pulse load current (from no load to full load) and observe whether the ldo can regulate the output or not...... also, check out for voltage during current trasition (oscillate)
Re: Substrate contact
One of the substrate tap function is to collect substrate current... so, if the design is sensitive to the substrate current i.e RF, u better put ur empty space with substrate tap other than decap.....
mosfet capacitance measurements
the small length effect cause the differences..... normally, the overlap cap is charecterised by using 10/0.35 for ur case......
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