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Hi, I am designing a VCDL at 7Ghz. I have selected current starved architecture. I am required of a delay of 150ps that is one cycle delay. i am getting 35ps delay with 4 stagesbut, as i increase the number of stages the output is attenuated after 7 stages. what might be the reason?
Hi,
I want to design a clock and data recovery circuit at 7gbps using 65nm technology. which cdr model is best to design? Is it the single loop or dual loop one? I need a phase frequency detector and i thought of designing binary detector. Please help me with it? and help me if there is any...
Thanks for your reply.. It works fine at my frequency and the problem was with the supply voltages. They use standard supplies available from the kit within the standard libraries. Delay is around 30ps.
I am designing a PFD and for the reason i am planning to use the standard D Flip FLop available in the KIt. But when i try simulating a DFF at 6.667Gbps. It was not working. Can someone help me with the reason for the problem. It shd work actually work as the 65nm technology has a very high Ft.
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