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Recent content by paulr127

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    UVC for FPGA Internal side

    Hi Besides other UVCs; I have been asked to make universal verification component(UVC) for FPGA Internal Side... What does that mean and why is this needed. Is this for scorebaord comparison?? Thanks very much
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    testbench without a DUT

    Thanks. Sorry inputs of what to outputs of what....
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    testbench without a DUT

    Thanks very much for all your replies. I appreciate that. I would appreciate if someone can give me example code of this fake dummy DUT which you have used or come across? Many thanks
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    testbench without a DUT

    I understand that. I meant can I have some sort of dummy dut to serve the purpose . Or we can have two UVM agents (one active and one passive) just to test connect them back to back wihout any dut.......
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    testbench without a DUT

    Thanks. I am new to this. Partcularly in UVM, how to make a testbench without a design/or DUT or more precisely making a testbench before the design is there and make sure it works....so that when design is available you can just instantiate it and use the same testbench.... Any example...
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    testbench without a DUT

    Hi guys Any tips on making a tesbench (UVM) before the design/DUT to start with?? Many thanks
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    Simulating Xilinx smpte sdi core

    Thanks very much. BTW what does this expression mean in verilog v <= # DLY line < first_active-1;
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    Simulating Xilinx smpte sdi core

    BTW Thanks for all your help. I was able to simulate in vivado. What do I need to do if I want to simulate in modelsim/questasim. thanks very much - - - Updated - - - The problem is I don't see the log file (it is not there in sim dir simulation.log is empty) and the messages about testing the...
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    Simulating Xilinx smpte sdi core

    Thanks very much for all your help. This was exactly what I needed - - - Updated - - - Hi Paul thanks for your response. I am able to simulate it but not using the way you described and would be interested to replicate that... When I right click (.......xci) file I don't see the option of...
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    Simulating Xilinx smpte sdi core

    Hi everyone, I have generated this core in Xilinx Vivado. It has a demo tb.... Can anyone guide me how to simulate it??Can't figure out what files to compile(design files). Many thanks
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    hd-sdi interface testing

    Thanks very much for this.Most/All of the example links are not working
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    hd-sdi interface testing

    Honestly. Not completely and carefully as yet( Just a glance yet)
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    hd-sdi interface testing

    Thanks for your reply. I would appreciate if you can point me to some reference bus functional model (if not particularly this) one so that I can get some idea of making those. Many thanks
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    hd-sdi interface testing

    Thanks very much. Can anyone help me with its Behavioural Functional Model please? Many thanks
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    hd-sdi interface testing

    Hi everyone I need to test a design which has Xilinx SMPTE SDI Core which had HD-SDI interface..... It goes to rest of the components.... I am not conversant with it. I have been asked to mimic that interface in my testbench and use the signals coming out of it as an input to test other...
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