Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
If you have a look a this... The TV is displaying all lines when I connect the shift register lines to a random counter...
This means theres no problem with VSYNC because if VSYNC was happening half way I'd be missing some lines...
Actually I'm pretty sure it isn't the VSYNC, I say this because I have tinkered the ram addresses just to see what happens and the screen starts to fill with data. It's only when the addresses into the RAM are correct that there is a blank area on the screen.
If VSYNC was incorrect, the screen...
Hi friends,
I have finished a circuit that generates composite video and it's almost*** working perfectly. Apart from some ultra weird problem that is occurring when data is displayed. Basically the system sweeps the RAM from address 0 to a certain final address. Each line is 8 pixels in...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
