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You are talking about the Voltage Aware simulations rather than the PA. I dont think any of the digital simulators (MVSIM, Questa-PA, or Verdi-PA) will support the Voltage Aware simulations. You cant really distinguish between the voltages and the same will not converted inside the design to...
Hi,
Please revert back if the PA experts who can comment on the Power Aware GLS with the Questa Sim.
There are some difference like the way Questa taking the Hard Macros as different optimisation and the visibilty to the design is removed while elaborating. If anything critical, known are shared...
Error suppression switches are different in different simulators. If it is Questa, use "+nosdferror" with vsim command. eg: "vsim +nosdferror +sdf_verbose"
Re: How to sdf back-annotate asynchronous paths in a multi-clock design
If you are doing only CDC path to get SDF annotate, and not considering the other part in GLS then you may get functional failures itself due to timing issues. These functional FAILURE would not actual failure itself. This...
You cant straight away force the memory content. Instead you can do simulator commad to dump the memory content. If you use NCSIM "memory -dump ..." is the option, similar to your tool identify the command, once you dumped the txt file modify the memory content and reload again to the memory...
Very simple reason is your output declaration "output [3:0] count" should matched with your reg declaration. It should be "reg [3:0] count".
Otherwise as per your code, reg assignemnt on single bit and your counter could not proceed further.
-paulki
Booting Sequence in SoC/ASIC
In any SoC/ASIC will have atleast One Master Processor (ARM/MIPS/MicrController) to control the Data path and Control path. ARM based SoC are common in nature nowadays and better to explain in ARM points of view, but still applicable for any Master Processor.
1...
Think thrice !!!. Google about the Company's current position and take inputs from friends.
If you are a fresher they will give good training. if you are experienced and considering about the growth and future.... better take frank opinions from the industry friends.
-paulki
Hi Juliog,
As you explained nicely. You are targetting Typical Corner "fsa0a_c_sc_tc" but you might forgot the corner in the correct format. It would be something like below.
set_operating_conditions -min BCCOM -max WCCOM -min_library fsa0a_c_sc_bc -max_library fsa0a_c_sc_wc -typ TCCOM...
"X" is a simulation debug feature to identify where the contention or unpredictive state comes. In actual silicon as you all said there would not be any "X". Only valid value either "0" or "1" based on the cell or memory charecteristic (Vendor based). In memories (except ROM) some specific...
Hi folks,
I need I2C and I2S protocol checkers (which is available without any company confidentiality). If anybody uses such open source code please share the same.
More interested in modelling the "Timing" models of the I2C Master/Slave models as well as checkers.
-paulki
Hi folks,
I need a help in enhancing my existing testbench with additional functionality. Want to know whether VHDL allows us to use compiler time defines ? ( like Verilog supports as `includes). If any such options are available please share with me. Appreciate all your inputs.
Thanks,
Paul
Hi techies,
I'm using NCSim for my current project (09.20-s025). I need to view the memory contents which is pre-loaded in the GUI Simulation. As we know with Modelsim has simpler tool to display memory contents, do we have any sub tool in NCSim to view the memory contents?
Here are my queries:-...
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