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Hi all,
I am now working on a project that maybe use the hybrid architecture with 1st stage CT INT(Gm-C INT) and DT INTs for other stages. I don't have the experience of designing a CT DSM or a Hybrid one. There are some questions about this kind of architecture.
1, How to realize the CTINT...
Hi all,
I am now designing a 14bit SAR ADC, at present, I have designed a prototype with ideal comp and sh. I run transient analysis with stop time 1s (10kS/s sampling rate), around 10000 samples, then I perform FFT analysis in MATLAB with window functions like hanning. However, large...
Hi,
I have a compilation error when I run pex in calibre. The error is shown in the pic.
I find the "nsd" in the rule file provided by foundry, however i think this error isn't related the rule file. Could anyone give me a hand? Thanks in advance!
Hi guys, I'm using the verilog-XL for mixed signal circuit simulation, however the simulation failed due to following error:
I found in my cds.lib, the software path definition has some problem,when i use "nchelp -cdslib" to complie the following cds.lib file, it happens as the third pic. Its...
Hi,
I want to design a LNA with low NF, using the architecture in Federico's paper "Wide-Band CMOS Low-Noise Amplifier Exploiting Thermal Noise Canceling", However, i am a freshman and it's my first time to design LNA.
I wonder, how i can achieved NF blow 2dB, while maintains large...
Hi guys,
I have some questions on bootstrapping technique in improving the OPA input impedance, as the figure shown below, how to explain the input impedance is bootstrapped by the CF? Thanks in advance!
Hi all,
How to improve sar adc's performance by thermal code method, what's its ads comparing to binary code, any advice or related papers are expected, thanks at advance!
Hi guys,
I am now design a sar adc mainly used for implantable devices to detect bio-signal, such as EEG. I wana know how to test sar adc, because i have already set up all the blocks, and what's the important specifications i should pay attention to? In addition, any one who can recommend...
Hi,
I am a freshman in designing a FDA with CMFB. I am now reading the Sansen's book and occurs many questions, it seems a tough thing for me to really understand this book.
There is some question about CMFB,
1. What's the function of CMFB, how it works?
2. what's the...
Hi,
I'm reading Sansen's Book, and occurs several questions. it's about the second non-dominant pole in current mirror in M3, I wonder how to calculate the pole, any convenient method to determine the value? and why the f_zero = 2*f_pole?
The slide is below. Thanks in advance!
But how can i estimate the offset by the current of two transistors? When many delay unit series togeter, how to estimate the offset using this method?
I have simulated the circuit, the comparator can achieved high resolution and can settle with one clk time. because of the output delay, i.e 100ns or more after clk settled to 1, I cannot plot input vs. ultimate output status in cadence.
Hi all,
I met a problem to test the offset of a V-T comparator, This kind of comparator converts the input difference voltage to time delay, now i wanna use Monte Carlo to test the offset of this comparator in ADE. I let the input voltage changing from -10mV to 10mV, and use the dc sweep to...
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