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1.source follower? kind of weird, i dont think level shifter works under saturation region. It's more like a digital cell, with its node voltage switching between VDD and 0v.
2.positive feedback... nah, the first one IS a positive feedback circuit too.
3.My opinion is, the second lv shifter...
i've done that in .tran simulation,it did work.
but i can't do that in .dc analysis, and in a power down mode,there shouldn't be a pulse at input.
well actually it can be fixed by modifying the latch, i simply don't know why there's a steady op point between 3.3 and 0 at the output.
It's a...
Dear all,
i have build a cross coupled circuit for my compator, just like the one in the fig.
here's my problem:
i've run dc analysis
when the input (i.e latch_p and latch_n) is at the state of (3.3V, 0v) or (0V, 3.3V),
the circuit works fine.
but when the input is (0,0), which should be the...
i am working on a 12 bit SARADC(4bit R 8bit C architecture), and get confused on the 4it R_DAC layout plan
fig1-> simply place R1 to R16 from top to bottom, no center-centroid, clear routing
fig2-> center-centroid layout, but the routing is killing me
R1~R16 are 2x20 um2 poly resistor
fig2...
I am currently working on a low speed SAR ADC(around 10KHz sample rate)
is it possible to get a 12bit resolution with 6bit(from resistors) + 6bit (from capacitors)?
i know it's possible to get 10bit from poly resistors, but not so sure about capacitors.
wow,you pre-answered my question before i ask it.
ya i am using a SC CMFB structure,
does it mean i should replace the CMFB op with an ideal one(infinite gain OP)?
or just bias the whole circuit in saturation and run AC analysis?
when doing .ac analysis for a single-ended OPAMP, we put a "ac 1" source at VINP, "ac 0" at VINN. then we can run simulation for gain and phase.
But what do we do when it comes to a differential OP?
put "ac 1" on both VINN and VINP , and probe (VOUTP - VOUTN) to see the OP's gain and phase...
resolution comparators
tks a lot!
i've thought the "offset+ resolution" idea,but can't be sure.
Also, the paper is great. thanks!
Added after 4 minutes:
i dont get it. I thought that offset and resolution are independent from each other?
1.5 bit adc, comperator
thanks for your reply!
one more question
i've read many papar said that in 1.5bit struture ADC, comparator "offset" can be tolerated up to 250mv(for 1V p-p input signal)
what's the difference between this "offset" and "resolution"?
comparator resolution
I know that for a N-bit flash ADC, it's comparator should have resolution higher than 1/2^N
but when it comes to a N bit pipeline ADC (1.5bit structure), does the same rule apply? or this requirement is somehow relaxed?
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