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Recent content by param426

  1. P

    Generation of clock in ADC

    Hi, I had output voltage from solar panel, i want to connect that output to ADC but ADC require clock frequency.... can any one give me suggestion to how clock will produce in that ADC.... thanks...
  2. P

    verilog code for sawtooth waveform

    RAMP WAVE GENERATION Code `timescale 1ns / 1ps module Ramp(Ramp,En,Clk,Rst); output reg [7:0] Ramp; input En,Clk,Rst; always@(posedge Clk or posedge Rst) begin if (Rst) Ramp<=0; else begin if (En) begin Ramp <= Ramp+1′b1; end end end endmodule This is ramp wave code, could you please modify...
  3. P

    verilog code for sawtooth waveform

    Hi, thanks for reply my question... here iam attaching the Block diagram.. i want to generate a sawtooth wave form with 100kHz in 50MHz FPGA board to compare with the MPPT out.. MPPT output is a sinusoidal wave .... plz FIA..
  4. P

    verilog code for sawtooth waveform

    Hi, Can any one suggest verilog code for sawtooth wave form.? thanks for spending time for read my question.
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