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You need not provide the pin number information while inserting the core.
Insert the signals u need to tap, trigger, sampling clock, depth... compile the design again and then analyse thru chipscope analyser. Pls check the appropriate manual...
Hi all,
Can anyone suggest to provide the delay after the cpld is programmed.
My logic has to work after 3 ms once the device is programmed.
Is it good practice to generate the counter for 3 ms, wait for it and then trigger the
design signals or is there any settings in compiler(Quartus II) to...
Speed grade will be selected when we choose the FPGA for our design.
Having different speed grade on ur software and later differnt speed grade on ur FPGA doesnt work...
the netlist created by the tool will be matched to the speed grade of the device chosen, so better to compile the code to the...
Re: help to create picture on memory and display on vga moni
Hi,
just for basic functionality test,
Put high/ low on the RGB lines.
Create a colour pattern of some lines of red,few green and blue.
like generate a band of colours on the display.
With colour pattern first u try to debug...
This...
vga vsync signal
Hi,
VGA standard is 640 X 480.
Hence there should be 480 hsyncs within in one vsync
and 640 pixels in one hsync.
The period for 640 pixels is represented as high on Blank signal.
The Formula which relates thepixel clock, frame rate,Hsyn and Vsync are
Horizontal Sync...
Re: Wrong output while trying to use module repeatedly..Help
Hi,
this peice of code i got from net...
Verilog algorithmic level model
module GCD_ALG;
parameter Width = 8;
reg [Width-1:0] A_in, B_in, A, B, Y, Y_Ref;
reg [Width-1:0] A_reg,B_reg,Swap;
parameter GCD_tests = 6;
integer N, M...
ip core ddr controller
Hi,
did u try what i have said...???
first open the modelsim...
then change the directory to the path where the modelsim folder is generated by the core.[u can change the directory by open modelsim->Files->Change Directory->browse the folder said]
Then type "set...
altera ddr2 controller simulation
Hi,
first change the project directory of modelsim to project_folder -> testbench->modelsim.
then in command window type the following.
set memory_mode_xxx.v
where xxx.v is the behavioral model of the memory you are using.
source yyy.tcl
where yyy.tcl is...
Hi,
thanks for the reply. Now, i could simulate the core properly, i had to instantiate the memory model twice in my application, which solved the simulation isuue. Please can you guide me how to control the speed of the read/write. I have to set the memory clock while generating the core...
Re: Plz help me...
Hi,
Try this: Go to Assignments -> Settings -> Analysis and synthesis -> On the "Auto RAM Replacement" Option.
OR the best way is to use the megafunctions provided by Quartus, where in you can specify the size, width and type of memory block.
Go to Tools -> MegaWizard...
Hi
I have followed the document generated from the core wizard. But i could not get the result for read operation[read data is in Z - state]. I have instantiated the micron memory model in the generated testbench. Will you please guide me in simulating it and the things to be taken care for...
Hi All,
I am using the ddr2 core generated through MegaWizard function from Altera Quartus II. Please help and let me know if any one have earlier experience in using it. I need some support in simulating it.
Thanks
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