Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by parafux

  1. P

    32 bit left shift of a longint variable does not work

    Hi all, I have two integer variables scaling_0 and scaling_1 I want to attach them so that scaling_0 are the lower 32 bit and scaling_1 are the upper 32 bit. The result should be stored in a longint variable scaling. I try this: scaling = longint'(scaling_0) + (longint'(scaling_1) *...
  2. P

    Systemverilog type cast or integer division

    now i found a solution that works properly for me, but i dont know why the approach above does not work pos1_x_1 = int'(pos1_x >> 32)
  3. P

    Systemverilog type cast or integer division

    Hi all, i am quite new to systemverilog. I normally code in VHDL. Now i have to do some test bench codings in systemverilog. I want to get the upper 32 bits of a longint variable. I do this: pos1_x_0 = pos1_x % (2**32); // lower bits, works pos1_x_1 = int'(pos1_x /...

Part and Inventory Search

Back
Top