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Hi all,
I have two integer variables scaling_0 and scaling_1
I want to attach them so that scaling_0 are the lower 32 bit and scaling_1 are the upper 32 bit. The result should be stored in a longint variable scaling.
I try this:
scaling = longint'(scaling_0) + (longint'(scaling_1) *...
Hi all,
i am quite new to systemverilog. I normally code in VHDL. Now i have to do some test bench codings in systemverilog.
I want to get the upper 32 bits of a longint variable.
I do this:
pos1_x_0 = pos1_x % (2**32); // lower bits, works
pos1_x_1 = int'(pos1_x /...
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