Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Sir The project is a part of the sonar receiver.Where the receiver receives Sound waves as input and those sound waves need to be transferred to digital. For this purpose A FPGA and ADC is used.The receiver is an hydrophone array.
I am quiet confused with one particular thing.I was instructed to write the coding for the timing diagram (Parallel interface) of AD7656.My doubt is the in the timing diagram the last signal is the transfer of databits DB0 to DB15.But the diagram portrays as if it is sending analog signals such...
sir,Actually they told to study the parallel interface(AD7656) timing diagram and the Altera max II CPLD has to generate those signals to ADC(AD7656).This is the information they gave me.And I really dont know what to concentrate and where to concentrate also.
In the data sheet(AD7656) they have not given any specific protocol and I am Using Altera Max II and regarding width I dont understand what is width in parallel interface
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
