Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by pandit_vlsi

  1. P

    calculate max freq and hold

    Hi Jitendra, Increase the delay of the combo logic by 100ps. Then we can make the circuit to work. Pandit M
  2. P

    some interview questions--answer needed

    Answer for the 4th Question: Assume that two register are 8 bit long. Connect the output of first register to the input of the second and connect the output of second register to the input of the first. Now do the left shift or right shift 8 times. Regards, Pandit.M
  3. P

    What do the vsim-SDF-3438 warnings mean?

    Hi All, i am annaotating SDF into my design. After simulation i am getting the warnings with code vsim-SDF-3438. can i know 1. Why these warnings have surfaced? 2.can i ignore these warnings? Thanks, Pandit.
  4. P

    LOCKup & SYNC Registers.

    synchronizer versus lockup latch hi cheelgo, MTBF?
  5. P

    LOCKup & SYNC Registers.

    lockup latch Hi all. 1.what are LOCK-Up flops/latches and sync registers? 2.when they are used? 3.what is the advantage? Providing pictorial explanation is appreciated. thanks a ton, pandit
  6. P

    verilogout_no_tri ---Need help for this command.

    verilogout_no_tri hi all. i am not following what this cmmanr will do. verilogout_no_tri Declares three-state nets as Verilog "wire" instead of "tri." This variable is useful in eliminating "assign" primitives and "tran" gates in the Verilog output.
  7. P

    Is there anything like Memory Synthesizes?

    hi all. Is there anything called Memory Synthesizes. and in SRams and RFs which gives good PPA. Thanks a lot... pandit
  8. P

    Tracks of a standard cell.

    Hi all. I have three doubts regarding tracks of a standard cell. 1. What are tracks? 2. What is the use of these tracks? 3. If we increase the no of tracks how it will improve the performance? Plz spare some time to answer these queries. regards, pandit.
  9. P

    What's the use of free-running clocks?

    hi all. i am working placement step in asic flow. i come across a word free-running clocks. what is the use of these clocks.... why those r removerd while CTS. thanks in advance. Pandit.
  10. P

    what are delay cells.when they are used in the ASIC Flow.

    Re: what are delay cells.when they are used in the ASIC Flow how are they diffrent from any normall cells.
  11. P

    what are delay cells.when they are used in the ASIC Flow.

    hi what are delay cells.when they are used in the ASIC Flow?. why we dont use them in Synthesis stage?. regards, pandit.
  12. P

    suggest some link for set-up and hold time questions

    hi folks. i want some problems relating to set-up and hold violations. plz suggest some links to get the questions. reards, pandit
  13. P

    what is temperature inversion

    temperature inversion asic hi all. i want to know about temperature inversion. plz dont say that as temp/ increses delay decreses in 90 nm and below. plz elaborate. pandit
  14. P

    in what case we consider the hold time violation

    hi kil. yes u are right hold time is not used in the calculation of Time period of the clock. but Hold time signifies " how fast the launched data is reaching the capture f/f at the same edge of the launching clock" which directly affects the next state of the capture f/f. pandit
  15. P

    Relation between temp and setup, hold and delay

    What is more probable to fail (setup or hold) at the following temperatures? 1. 125 °C 2.-40 °C & in general delay. regards, pandit

Part and Inventory Search