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Answer for the 4th Question:
Assume that two register are 8 bit long. Connect the output of first register to the input of the second and connect the output of second register to the input of the first.
Now do the left shift or right shift 8 times.
i am annaotating SDF into my design.
After simulation i am getting the warnings with code vsim-SDF-3438.
can i know
1. Why these warnings have surfaced?
2.can i ignore these warnings?
i am not following what this cmmanr will do.
Declares three-state nets as Verilog "wire" instead of "tri." This variable is
useful in eliminating "assign" primitives and "tran" gates in the Verilog output.
I have three doubts regarding tracks of a standard cell.
1. What are tracks?
2. What is the use of these tracks?
3. If we increase the no of tracks how it will improve the performance?
Plz spare some time to answer these queries.
yes u are right hold time is not used in the calculation of Time period of the clock.
but Hold time signifies " how fast the launched data is reaching the capture f/f at the same edge of the launching clock" which directly affects the next state of the capture f/f.