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Hi everyone!
Is there any reliability issue when using a MOSFET as a decoupling cap for the supply voltage line?!
The gate will be connected to vdd, and source/drain will be connected to ground.
My concern is the gate terminal connected to VDD.
Thank you very much.
Thanks guy for all contributions.
There is a input pin connected in a CMOS inverter that will receive a signal of 1 MHz. And the output pin is connected in a open-drain transistor, whose output signal will be around 1 MHz too. In this case, we are going to measure it using a high-impedance...
Hello guys,
I'm designing a simple IC with a signal around 1 MHz. Can I measure it if my IC will be packaged with DIP?
What is the maximum frequency (without attenuation) of a signal that can be measure in DIP packages?
Thanks and best regards,
Basic question about commom source amplifier with inductor
Hi guys,
In the figure, the resistor RD is replaced by the inductor LD, RAZAVi says that the new circuit has better frequency response. Could, you please, explain why?
How does the Module of Bode diagram looks with the indutor...
Hi guys,
Could you give some example of journal/periofical that we can submit our paper regarding Wireless Energy Transfer ?
The work is in its first stage and it is still not good enough to be submitted to the best journals and IEEE transactions.
Thank you very much,
Re: Basic question about layout (commom mode centroid configuration) - current mirror
Thanks guys for all replies.
I guess it was possible to achieve a more compact layout doing in this way, and then, a better layout matching
I think I'm going to layout my next DC circuits in this way!!
Re: Basic question about layout (commom mode centroid configuration) - current mirror
why? in digital circuits, ok (there is a speed issue). How about this case? I´m worry about matching.
FvM.
You are completely right! I have increased C1 and the -3dB corner frequency became the one I have expected before, when I have applied the Miller theorem. ( about ~ 8 kHz).
Why did the pole move to that one we expected? What did you have in mind when you gave your suggestion?
Is it related...
Thanks, FvM!!!
Why should I look what happens on the input side?
I mean, why does (CX) affect the output pole?
The output pole only depends on the output capacitor, doesn’t it?
Since the simulated -3db frequency is a about 20 kHz, it is like CY is lower than C3 (and I did not understand that)...
Hi guys,
Please, consider the attached circuit.
Based on the Miller theorem, C3 (miller capacitor) can be divided in two capacitors connected to ground. The first one (CX) is connected from node 2 and ground, and the second (CY) one is connected from node 3 (vout) and ground.
The capacitor CY...
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