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For item 4 you can measure the ground or Iq current with no signal on your bench using a current probe as barry is suggesting. If it's very low you're device should stay relatively close to ambient temperature. But if it's running current your junction will be greater than ambient.
Hey all,
I am a test engineer looking to learn more about design LDO regulators. I have a bunch of books I plan to start pouring through but I was wondering for those with experience on this board where you started out your career. I will be working in a sub micron process with a max load...
My suggestions:
1. What type of package should I choose, (DIP or QFN or others)? It seems that the long bonding wire of DIP and the resultant parasitic inductance may degrade the performance of the LDO.
I would recommend SOT. Very easy to scoop and goop and it is a standard package across the...
Hi guys and gals. I have put together a PLL that takes a 40Mhz reference clock and output a 2.56G signal. It must lock within 1.5uS. My phase detector and charge pump are based on the one in this paper.https://www.eurojournals.com/ejsr_33_2_05.pdf
My problem is that my vcontrol latches up...
Hi guys. Does anyone have a simple topology recommendation for converting the differential output of my vco into single ended so I can feed it into my integer divider? Thanks!
Hi sorry for not responding quickly. I am trying to determine the gain so that i know how to adjust my loop filter. This VCO is part of a PLL using a FE-PFD and a divide by 64 using 6 TSPC circuits.
Hey guys and gals, I am trying to simulate the parasitic resistance of a spiral inductor. I have enclosed a picture of my schematic. I try running ac analysis sweeping a frequency range. That goes off successfully. I then tried calculating the resistance of the inductor by going to calculator...
Thank you for the help so far. However I will be honest in saying I have no idea how to simulate my circuit.
I found a different version that uses just an input with no clock.
I went into the analog design and set my vdd to 1.2, and gnd to 0. For "D" input, I chose a pulse initially 0 that...
Hey again everyone. I have a quick question about PLL's again. How do i determine my required KVCO.
I have the following equation for overall gain
K(phase_detector)*K(loop_filter)*K(vco)/N
I have calculated I need my overall look gain to be 4.8e6. My loop filter gain is 300k. My divider value...
Increasing gm of driving transistor of a stage increases gain, decreases bandwidth
Increasing Id increases bandwidth, decreases gain.
You should also be careful if using a common source stage as second after a differential pair. The miller effect can absolutely destroy bandwidth.
But there are...
Hey guys and gals. I am trying to design a frequency divider for my pll. It needs to divide a 2.56Ghz VCO output back down to 40Mhz.
My plan was to use simple CML latches and put 6 in series with one another to get the divide by 64 I need. However, my professor was quite fuzzy on the details of...
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