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Recent content by oursriharsha

  1. O

    fuzzy control of pid controller

    Re: pid controller vhdl code can you please provide any documentation of the same , for further understanding. Thanks in advance.
  2. O

    Xilinx CPLD XCseries power

    Hello , can u please give me some info regarding , what way is there to find the maximum that a CPLD takes (XILINX) 1) How does the Power (the maximum) consumed by a CPLD (preferably Xilinx) i have gone through the Google , for the same and also the vendor's site , the terms were confusing...
  3. O

    vlsi design tools- description, basic tools, good websites

    vlsi design tools Hi Can anyone please tell me what exactly can we do with the Cadence , virtuso , and other tools. 2) what are the basic tools one should know, if , one wants to his career with the VLSI design. 3) Can u please suggest some good sites that give an overview of different...
  4. O

    Tools : Cadence, virtuso, cadstar etc , etc.

    Hi Can anyone please tell me what exactly can we do with the Cadence , virtuso , and other tools. 2) what are the basic tools one should know, if , one wants to his career with the VLSI design. 3) Can u please suggest some good sites that give an overview of different tools for different...
  5. O

    FPGA Board with some ADC

    adc fpga board Is it that you want an FPGA with more than 4 Analog I/O s you mean to say ? and if it is so , you can opt for Fusion device from Actel with 600k gates and 30 Analog I/Os. (AFS600)
  6. O

    communication problem between two FPGA board through UART

    UART -help Hello , I m trying to communicate between two FPGA board through UART , a constad data of 16 byte is being transmitted from the board1 with a baudrate say 9600. and the other board is also configured to receive at the same baud rate, i m trying to receive the 16 bytes of data and...
  7. O

    need CPLD tools to practise or synthesis tools

    CPLD tools ?? Can anyone suggest the best tools to practise or to look for a LATTICE CPLD / any synthesis tools for CPLD ???
  8. O

    AES CORE (128/192/...) URGENT ! PLS

    Can anyone help me with an AES core (128/256) , other than from opencores? or if from open cores , help me in how to extract the files . Thanks in advance
  9. O

    AES Application - ACTEL FUSION FPGA- 40 points for help

    application of fpga I need still some more ideas on this AES PLZ!
  10. O

    AES Application - ACTEL FUSION FPGA- 40 points for help

    fpga aes Nice to see the replies , but dear friends, i need some ideas how i can demonstrate the same. Usage and availability of cores, i agree that they are available on the opencores. Kudos tariq, for the suggestion of the easy one,
  11. O

    VHDL Syntax error in Modelsim simulator

    Re: VHDL Syntax error else if(count <= 55) then parallel_data(count-1) <= serial_data_in; count := count +1 are any other set of conditions you rae checking in the else conditions ? please check the syntax elsif instead of else if (...... .... . .. ) please do let me know the...
  12. O

    AES Application - ACTEL FUSION FPGA- 40 points for help

    actel fusion Hello I m currently interested in coming up with a Small application based on AES to implement and verify through ACTEL FPGA - Fusion device. How one can show the encryption and decryption ? Can anyone give me some more idea as i am a lay man regarding this. Please do help...
  13. O

    wcdma using vhdl coding - please help

    wcdma design using vhdl checked opencores ?? :)
  14. O

    Post synthesis Vs pre synthesis

    i get X s in place of data..

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