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Recent content by osbourne

  1. O

    Study material regarding practical PCB production

    Hi, i need papers documents about PCB manufacturing, especially about the meaning of the different layers (silkscreen, soldermask, solderpaste, prepregetc.). Information about soldering processes would be also helpful, especially wave soldering and reflow soldering. Please send documents...
  2. O

    Transformer for electrical isolation

    desk electrical isolation Hi, does anybody have documents about transformer applications, especially about electrical isolation ? I've read, that electrical isolation is sometime necessary due to grounding problems. I'd like to have some detailed explanations about how these grounding problems...
  3. O

    Fujitsu MB90F352S and accemic debugger

    accemic 2006 Hi, I've developed a microcontroller software that communicates with a PC via the UART2 of the Fujitsu MB90F352S microcontroller. For development I also use the ACCEMIC debugger. Problem: Communications works as long as I work with the debugger (bootloader of debugger +...
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    Difference between PLD, CPLD and FPGA

    difference between pld & fpga Hi, can anyone explain, what's the difference between these 3 device families. What can be done with each and what can't ? Thanks, Osbourne
  5. O

    Peak-to-average reduction techniques

    Hi, I need a method to reduce the peak-to-average ratio of multicarrier signals (e.g. 4 carrier UMTS signal) from about 11 dB to ~5.5 dB. I used a method called peak windowing, which results in a reduction to 7 dB. Is it possible to get a better result ? regards, Osbourne
  6. O

    VHDL code for LMS algorithm

    lms vhdl Hi, I need VHDL code for LMS alsgorithm. Can somebody help ? Thanks
  7. O

    FPGA implementation of LMS algorithm

    fpga implementation of the lms algorithm Hi, has anybody ever implemented the LMS algorithm in an FPGA ? I don't know how to choose the different wordlengths throughout the LMS calculation steps. Does somebody have VHDL example code or does somebody know, where to find it in the internet ...
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    Xilinx Floorplaner and FPGA Editor

    fpga editor tutorial Hi, even if it is not much used, I'd like to learn how it could be used. How can I learn it ? My design is very large and there are hundreds of lines and hundreds of placed components. I cannot imagine what could be done using FPGA Editor because I don't know the meaning...
  9. O

    Xilinx Floorplaner and FPGA Editor

    fpga editor Hi, I'm a beginner in FPGA design. I'm currently asking myself, if Floorplaner and FPGA Editor are really needed to make an FPGA design. Are these tools rarely used or is there somebody who extensively uses them? In which situations shall I use them ? If I have a very large...
  10. O

    Xilinx Fast Fourier Transform v3.2 IP Core (Virtex II FPGA)

    Hi, has anyone experience with the FFT IP Core of Xilinx ? I think there is a bug in this IP Core. When I process a continuous data stream, everything is OK. But when I stop the processing for a period of time and then restart it using the START input, errors occur. The error occurs in the five...
  11. O

    Clocking in FPGA Designs

    Hi, is it possible to use only one clock (DCM) for a large design, e.g. in a Virtex II device. As the design becomes larger, more and more devices are connected to the clock, which normally is not allowed in a digital circuit because of limited fanout. Or does the synthesis tool automatically...
  12. O

    Xilinx Multiplier V7.0 question

    I discovered something (which I do not understand: When I start the simulation of the placed and routed design within ISE, I get the mentioned "fast changes". But when I end the simulation and restart it within Modelsim the "fast changes" are gone ??!?? Hää Can I trust Modelsim/ISE ??? Added...
  13. O

    Xilinx Multiplier V7.0 question

    The interval of "fast changes" is about 0.55 ns whereas the clock period is about 10.9 ns. This should be no problem (hopefully) ?? Yes I know, there are thousands of signals when I simulate a placeed and routed model and I also often can't find the ones I'm interested in. By the way, I also...
  14. O

    Xilinx Multiplier V7.0 question

    Hi, thanks, you're very helpful. So, "posedge clk" generates the register ? I use VHDL and I guess I can use "rising_edge(clk)" to generate a clocked register, right ?
  15. O

    Xilinx Multiplier V7.0 question

    Hi, yes, I have registered the multiplier output. But I still have the mentioned problem. Did you see this problem too, when you use the Core multiplier ? The IP Core uses a 18x18 hardware multiplier of the Virtex II. Using a*a and b*b builds a combinatorial multiplier, doesn't it ?? Thanks...
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