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I have 2 USB devices that I would like to multiplex, that is according to the state of a selector S I would like to connect either USBdev_A or USBdev_B to a USB_PC. Obviously, GND is connected together, but V+ (5V) is routed outside the FPGA. So, I just need to multiplex D+D-
The main problems...
Thank you very much for all your suggestions. I really appreciate your help!
So far I’m employing as source a dedicated time code generator, so I hope I should not be concerned too much about variation in speed of the smpte code. My first goal is to develop something that ‘just work’. Once I...
Thank std_match for your suggestion!
This is a quick sketch of the ASM and datapath of the new decoder made using your help.
Everything that is done before incrementing the counter CNT serves as initialization (the FSM waits for the first data transition).
The sampling clock is obtained by...
Thank you very much for your help! :smile: and sorry for posting in the wrong section.
I have no practical experience in reconstructing a signal after performing sampling, do you have suggestion in terms of resources (e.g. books, websites)?
Would it be reasonable to implement the FSM in the...
Hello! :-)
I am a just-graduated engineer and right now I am doing an internship in Japan. My task is to develop a SMPTE time code decoder on a FPGA ALTERA DE0 TERASIC and display the time-code on the 7-segment displays.
I have attended two courses at the university about digital design, but up...
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