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thank you gag2000 ，I did some test and now have some finds.
Because this is a Asic，not FPGA， so I can't probe testmode. But I use a scope see the FCLK and DATA on the chip's pads. There did have some glitches on the two pads. Because the pads is not schmitt pads, so I think the circuit falls...
hello every body!
I met a strange thing on my chip. It goes into testmode very easily. By my design this is not impossible！
The testmode state is controlled by the following RTL code. It is very clear to go into testmode, we must add a complex wave form on FCLK and DATA, and any erro...
1-How many clock gating of this type do you have in your design?
There are about 20 this type cells. But only the one who's CK connected to PAD's input pin caused power consumption.
2- So the 1-2mA is only leakage power, as you indicate when CLK is high, the clock edge has no impact on the...
hi，every body！
I have had a lot of time on this question, but still have no answer now.
The chip is every thing ok but power consumption. By EMMI, we find the point cause the power consumption is on a clockgating cell.
And I find that only when CK is high will power consumption...
hello every one！
I have a gtech netlist and need to implement it on FPGA and on AISC Design. But now I'm not sure about the way I deal with it.
The way I choose is as follows :
Bcz the UDPs are not synthesisable, So I redescript all the UDPs in a synthesisable format. for example ...
FPGA timing constraints must be carefull, you should better put the clocks in the xilinx clock primitives, such as BUFG, BUFGMUX etc. this could be help.
hi rajesh6821,
In my opinion, The biggest FPGA vendor is Xlinx and Altera, if you have no very special reason, it's just ok to select from this two componies.
And I feel there is no big differences between Xilinx and Altera :)
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