Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by oratie

  1. O

    Multi stage ICG

    Root ICG cut off clock for the whole design. But, you can want to cut off clock just for part of design. During the real operation of your design some flops may not switching, so it is reasonable to stop clock propagation to these flops.
  2. O

    [SOLVED] Power bump connects to power stripes

    You shoud apply appropriate voltage to the bump connected to the standard cells (the power IO cells do not have any level shifter inside, only direct connection plus ESD protection). So, it is your fault if you apply higher voltage. There are no any differences between power and signal bumps...
  3. O

    min skew check

    Another example is "Source-Synchronous clocking". Clock signal delay can not be less than data signal delay.
  4. O

    min skew check

    For example: if you have zero clock skew, all flops will switch at the same time. It will cause big IR-drop.
  5. O

    [SOLVED] Power bump connects to power stripes

    You can connect bumps to stripes directly. Do not forget to add ESD protection (power cells or clamps ...) - see foundry DRM for details.
  6. O


    It is DFT DRC, not layout DRC.
  7. O

    Can two clocks from a parent partition enter a child block through the same port ?

    Yes, they can. But not at the same time. From STA point of view it is very common to have several clocks defined on the same point (port). But, you don not need to check/optimise timing path between such clocks.
  8. O

    SDC: How to set delay in a clock path

    In ICC2 you should use derive_clock_balance_points before CTS in order to respect set_clock_latency.
  9. O

    SDC: How to set delay in a clock path

    set_clock_latency my help you. Synopsys ICC read this command to adjust clock latency during CTS.
  10. O


  11. O

    Problem with Power nets

    No, it only means, that you have power (or ground) net VDD in the design. Option -all include power/ground nets in get_nets result printing. Information: connected 18799 power ports and 18799 ground ports - This means, that you have VDD/VSS connected to pins.
  12. O

    Problem with Power nets

    Try such command "get_nets -all VDD"
  13. O

    Is it okay to leave the MOSFET body as a floating node?

    It is OK using the 97nm. But 65 or even 130 - not OK. Read the manual.
  14. O

    NLDM timing model for I/O cells

    Instead of indices you can see tha name of indices. Look for this name in the header of libfile.
  15. O

    [SOLVED] Clock Gating Insertion Problem

    If -gate_clock option is not what you want, you can manually insert clock gating library cell (not the gating code) directly in RTL. And set_dont_touch on it before compile.

Part and Inventory Search