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Recent content by optor

  1. O

    [help] serial flash AT25F1024

    at25f1024 Does anyone here has the verilog simulation model for AT25F1024? I cannot find it in the internet. Thanks a lot!
  2. O

    A question asked to me in interview???????

    You can consider the floorplan as a pre-P&R process,just for a approximation of area and timing.
  3. O

    Pipelining Techniques

    Hennessy and Patterson's book 'Computer Architecture: a quantitative approach' is useful for you. There is download links for serval editions in this forum.
  4. O

    why usb2.0 speed up to 480Mb/s?

    For its high operating frequency, i think.
  5. O

    Can function be used in Verilog RTL?

    Re: function used in RTL Sure, but it is suggested that using function only in testbench.
  6. O

    How to solve Setup and Hold violation without reducing FPGA clock frequency?

    Re: FPGA Timing Rewrite your HDL code.
  7. O

    converting verilog code to gate level design..

    I guess FPGA companys can offer the library you need. Try their websites.
  8. O

    Motion detector examples for a room

    Re: motion detection You need a sensor more than 8051.
  9. O

    How to map virtual memory into physical memory using C?

    Re: mapping of memory That's a work of OS or computer architecture?
  10. O

    fundamental question about reset.

    xilinx asynchronous reset signal constraint The sequential circuits need a signal to enter an initial state that is reset. Syn-reset signal is always sampled at the edge of clock while asyn-reset not. I think the Synopsys on line document discussed such problem, you may refer to it.
  11. O

    set up time violations

    Set up time violations means the data is not stable when it is sampled by the next pipeline stage. Be carefor of the critical path.
  12. O

    Which bus interface is the best in the SoC or IP design? Wh?

    Re: Which bus interface is the best in the SoC or IP design? You can have your own bus architecture for your SoC. Try NoC concept?
  13. O

    Computer Architecture

    computer architecture+book+simple " Computer Architecture a Quantitative Approach" by Patterson.
  14. O

    8 bit register ( help )

    You want to find that chip?
  15. O

    critical path problem

    Firstly use Design Compiler to synthesis your design, the tool will give you results such as critical path. For your 2nd question, basically the longest timing path is the critical path. Primetime is a powerful tools to analyze the timing path. For you, the Design Compiler is enough.
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