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i read the protocol 3 times and I think i understand it.
Based on the protocol, the address decoder is combinational logic. its inputs are just the address from the master, so its outputs are in the same cycle with the address cycle. But ahb's data cycle is one cycle after the addr cycle. So in...
Can anyone explain the relationship between the operating frequency and the read/write access time in sram.
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find some answer from a manual and share the answer with guys here. but still have some question about this. Why access time can be larger/equal to...
I have a question about write operation of 6T sram
I know for sram read:
phy2 : Precharge both bitlines high
phy1 : Then turn on wordline, One of the two bitlines will be pulled down by the cell
for sram write, my question is that during phy2, does the bitline and bitline_bar need to...
I have a question about when the AHB can be deadlocked. I get this question in the AMBA protocol pdf from ARM but it seems that it's not clear enough for me. And I found something in the ARM information Center, which says:
Does a master need to issue non-LOCKed accesses when...
would you plz summarize the situations when case state will refer to priority encoder? I think I mess something up here.
it seems that without synopsis parallel_case directive, case and casez will always refer to priority encoder no matter whether the case items are parallel or not. but if we...
always @ (a or b or c or select2)
r = c;
2'b00: r = a;
2'b01: r = b;
in an article, it says this will infer a priority, but I don't think so. can anyone correct me if i am wrong.
this is just a non-full_case case statement, why it will infer priority. priority...
I still can not understand this pingpong effect. would anyone can post an example here? and more, why it create long layout-dependent timing path?
This forum is sooooo good, learn a lot here. will recommend my friends to join this forum.:grin::grin:
you said "assign two clock buffers". i don't quit understand this. do you mean if synthesis tool treat it as clk, then it will buffer it by default. I am wondering this because i read some articles and they says don't use data to connect to the clk of fflop because the synthesis tool treat them...
module which_clock (x,y,q,d);
always @ (posedge x or posedge y)
q <= 1'b0;
q <= d;
In this, how does the synthesis tool, figure out which is clock and which is reset. Is the statements within the always block is necessary to find out this or...
hello all, i read a article about blocking and nonblocking, it says that latch should be implemented using nonblocking assignment. but i don't know what's the reason for this. can anyone explains this a bit more. thanks in advance.